1. Field of the Invention
The present invention relates to a semiconductor device and an offset voltage adjusting method, and more particularly relates to a semiconductor device able to confirm adjustment values of voltage and current depending on a fuse connected/cut state before the fuse cutting and to an offset voltage adjusting method capable of confirming an adjustment value of an offset voltage of a differential amplifier before the fuse cutting.
2. Description of Related Art
In recent years, the number of electronic parts has increased in an automobile and a development of not only an ECU (Electric Control Unit) but also a PCU (Power Control Unit) has progressed. A role of an IC mounted on the PCU is a control of a load part driven with a large current (for example, a lamp of a headlight and motors used for sliding operations of doors and side mirrors). The large current must be accurately controlled.
It is important to reduce the offset voltage of an operational amplifier used in a system for controlling this large current with a high degree of accuracy. The offset voltage of the operational amplifier is generally generated because of a variation of elements on the manufacture, and can be reduced when a layout of the element is carried out by using a large area. However, in an IC which is requited to be miniaturized and to mount various circuits including the operational amplifier on one chip, an area for the operational amplifier is limited, so that the offset voltage sometimes cannot be sufficiently reduced. Consequently, an adjustment element is preliminarily mounted in order to adjust the generated offset voltage, and the fuse connected/cut states of the adjustment element are changed through the cutting of the fuse depending on the generated offset voltage to adjust the offset voltage.
In addition, in case of adjusting the offset voltage in a high accuracy, a desired adjustment value sometimes cannot be obtained because of the variation of elements on the manufacture even when the fuse is cut correctly in accordance with a design. For this reason, it is useful to realize an internal state equivalent to a circuit in which the fuse has been cut before the fuse cutting and to be able to know the adjustment value.
In conjunction with the above description, a related art allowing a confirmation of an output value after the fuse cutting prior to the fuse cuttings will be described below. In a semiconductor device in Japanese Patent Application Publication (JP-P2006-344793A), an internal circuit equivalent to a circuit in which the fuse has been cut, is realized by applying a voltage on a test node other than a node for the fuse cutting (hereinafter, to be referred to as a fuse cutting node). In a system requiring a high accuracy of the adjustment value, a fuse sometimes has a value different from a design value because of the variation of element on the manufacture. Accordingly, it is important to be able to know an internal circuit as an arbitrary combination of connected and cut fuses in a system requiring a high accuracy of the adjustment value.
A method for realizing a state of an internal circuit equivalent to a circuit in which the fuse has been cut without adding a test node is described in Japanese Patent Application Publication (JP-P2004-253676A). Referring to FIG. 1, a semiconductor device described in Japanese Patent Application Publication (JP-P2004-253676A) includes a fuse 102 connected between a node 101 to which a voltage V1 is externally applied and an N-channel MOS transistor MN100 whose gate and source are grounded via an output node 104 and a LED (Light Emitting Diode) 105. The fuse 102 and a drain of the N-channel MOS transistor MN100 are connected to a fuse cutting node 103. When the fuse 102 is cut, a current I0 flown from a source of the N-channel MOS transistor MN100 is 0 A. In order to establish a circuit state equivalent to a circuit in case of the fuse cutting without cutting the fuse, a predetermined voltage V2 is applied to the fuse cutting node 103 to withdraw the current to the fuse cutting node 103. Accordingly, the current I0 becomes 0 A to realize the internal state equivalent to the fuse cutting state. In addition, since the fuse cutting node 103 is a node used in the fuse cutting, there is no need to add the test node as described in Japanese Patent Application Publication (JP-P2006-344793A). In this method, an adjustment value of trimming (a current flowing through the LED 105) can be known before the adjustment and there is no need to add a node.
A semiconductor device described in Japanese Patent Application Publication (JP-P2006-344793A) requires adding a test node in order to realize the internal circuit state after the fuse has been cut to increase a circuit area. Meanwhile, without adding the test node, the semiconductor device described in Patent document 2 can realize the internal state after the fuse has been cut with using a cutting node.
However, in a case of realizing an internal state after a fuse has been cut, it is simultaneously required for a semiconductor device described in Patent document 2 to apply a voltage to the cutting node and to withdraw a current from the node. Since being set by a tester, a current value withdrawn from the fuse cutting node 103 can be a constant value. On the contrary, a current drive force (a current amount that a transistor can flow) of an element (the N-channel MOS transistor N-channel MOS transistor MN100) cannot be a constant value because of the quality variation, and there is a possibility that a desired configuration described above, the current value I0 is 0 A, cannot be realized. It is required to preliminarily measure the current drive force of the element and to change the current value I0 for each of circuits to be tested in order to change the current value I0 from the node depending on the quality variation of the elements. This leads to an increase of a test time. In addition, in a case where a current value of the LED 105 to be adjusted is small, an extremely high accuracy is required with respect to a current value withdrawn by the tester.